[Linux-Xtensa] SMP kernel with Xtensa ISS.

linux-xtensa at linux-xtensa.org linux-xtensa at linux-xtensa.org
Thu Apr 2 05:06:00 PDT 2009


On Thu, Apr 2, 2009 at 1:35 PM,  <linux-xtensa at linux-xtensa.org> wrote:
> linux-xtensa at linux-xtensa.org wrote:
>>
>> linux-xtensa at linux-xtensa.org wrote:
>>>
>>> Hello,
>>>
>>> I have found much Linux SMP kernel porting discussion in this mailing
>>> list. I would like to know is there anyone who uses the Xtensa ISS and
>>> XTSC environment for the Linux SMP kernel?
>>
>> What is XTSC? I suppose I should know.
>
> I just realized while driving home that your referring to the Xtensa
> non-GPL compiler.

Sorry, I should give the full name. XTSC means the XTensa SystemC
Modeling which can be used for system modeling and simulation
environment building. Please refer to the following web page:
http://www.tensilica.com/products/devtools/hw_dev/sw_xtmp_xtsc.htm

>>
>>>
>>> More directly, I have met a problem how to make the data cache
>>> coherent with the SMP architecture by using XTSC environment?
>
> I don't see why the compiler should effect the cache coherence.
> We were discussing modifying ISS to detect the data cahce having
> a cache alias.
>
Yes. You are perfectly right. I want to know how to modify the ISS to
provide a cache coherence protocol. Do you have some suggestions?
>
>>
>> I haven't tried the SMP kernel on ISS but I have make the data
>> cache coherent, even with non-small caches which typically experience
>> cache alias problems.
>>
>> The 2.6.27-smp git repo with our new external cache controller is quite
>> stable.
>> Possibly a bit more stable with larger caches with the alias issue.
>>
>> -piet
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>
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-- 
Hao Shen


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