[Linux-Xtensa] SMP kernel with Xtensa ISS.

linux-xtensa at linux-xtensa.org linux-xtensa at linux-xtensa.org
Fri Apr 3 02:19:51 PDT 2009


Hao Shen wrote:
> That really makes me sad. As I am an academic user, I don't know if
> this new version could be not available for me....

Perhaps you can re-apply for the next major release when it comes out?

Another possibility - given you are running in simulation, do you really
care about caches?  If you don't simulate caches, you might not need cache
coherency.  You still need some way for processors to interrupt each
other, and for the master processor to start the other processors.
And update SMP Linux sources accordingly, to use your mechanisms.
Involves a fair bit of work, both target-side and simulator-side.
I'm not sure what else might be missing, no one has tried this, so
I don't know if it would work really.  Can't think offhand why not,
but hey, don't think that means anything  ;-)

-Marc


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