[Linux-Xtensa] SMP kernel with Xtensa ISS.

[linux-xtensa at linux-xtensa.org]

On Fri, Apr 3, 2009 at 11:19 AM,  <linux-xtensa at linux-xtensa.org> wrote:
> Hao Shen wrote:
>> That really makes me sad. As I am an academic user, I don't know if
>> this new version could be not available for me....
>
> Perhaps you can re-apply for the next major release when it comes out?
>
> Another possibility - given you are running in simulation, do you really
> care about caches?  If you don't simulate caches, you might not need cache
> coherency.  You still need some way for processors to interrupt each
> other, and for the master processor to start the other processors.
> And update SMP Linux sources accordingly, to use your mechanisms.
> Involves a fair bit of work, both target-side and simulator-side.
> I'm not sure what else might be missing, no one has tried this, so
> I don't know if it would work really.  Can't think offhand why not,
> but hey, don't think that means anything  ;-)

I would like to have a data cache because it can provide more accurate
experimental results. The non-cache SMP may be also a possible
solution for me. Now, I will take a look how much work is necessary
to make it work. I don't know if MMU is also a problem?

> -Marc
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-- 
Hao Shen