[Linux-Xtensa] RE: [RFC 5/6] xtensa: add support for the XTAVNET
marc at tensilica.com
Tue Nov 6 13:08:53 PST 2012
Max Filippov wrote:
> The Avnet LX60/LX110/LX200 board is an FPGA board that can be
> configured with an Xtensa processor and an OpenCores Ethernet device.
This same platform now also supports the ML605, which a Xilinx board
not an Avnet board. So perhaps the platform can be named more
generically? eg. xtboard, or perhaps more specifically xtemul or xtfpga?
> Signed-off-by: Chris Zankel <chris at zankel.net>
> Signed-off-by: Max Filippov <jcmvbkbc at gmail.com>
> diff --git
> new file mode 100644
> index 0000000..ccdbca8
> --- /dev/null
> +++ b/arch/xtensa/platforms/xtavnet/include/platform/hardware.h
> @@ -0,0 +1,52 @@
> + * arch/xtensa/platform/xtavnet/include/platform/hardware.h
> + *
> + * This file is subject to the terms and conditions of the
> GNU General Public
> + * License. See the file "COPYING" in the main directory of
> this archive
> + * for more details.
> + *
> + * Copyright (C) 2006 Tensilica Inc.
> + */
> + * This file contains the hardware configuration of the
> XTAVNET boards.
> + */
> +#ifndef __XTENSA_XTAVNET_HARDWARE_H
> +#define __XTENSA_XTAVNET_HARDWARE_H
> +#include <asm/processor.h>
> +#include <platform/system.h>
> +/* By default NO_IRQ is defined to 0 in Linux, but we use the
> + interrupt 0 for UART... */
> +#define NO_IRQ -1
> +/* Memory configuration. */
> +#define PLATFORM_DEFAULT_MEM_START 0x00000000
> +#define PLATFORM_DEFAULT_MEM_SIZE 0x04000000
> +/* Interrupt configuration. */
> +#define PLATFORM_NR_IRQS 10
> +/* Default assignment of LX60 devices to external interrupts. */
> +/* UART interrupt: */
> +#define DUART16552_INTNUM XCHAL_EXTINT0_NUM
> + * Device addresses and parameters.
> + */
> +/* UART crystal frequency in Hz */
> +#define DUART16552_XTAL_FREQ (CONFIG_XTENSA_CPU_CLOCK * 1000000)
This requires setting the board frequency in the .config ,
which is a hassle. It means the kernel needs to be rebuilt
whenever resynthesizing the board to a different frequency.
This had been corrected in the platform port found on:
in branch marcdev, by reading the correct frequency from
an FPGA register. Was there any reason not to include
that fix? For example in that branch's setup.c :
/* Clock rate varies among FPGA bitstreams; board specific FPGA register
* reports the actual clock rate. */
serial_platform_data.uartclk = *(long *)XTAVNET_CLKFRQ_VADDR;
Note also, clock resolution in MHz is quite low.
Bitstreams are often synthesized with non-whole MHz
frequencies, eg. 41.666666 MHz, 33.333333 MHz, etc.
So computed divisors may not be optimal.
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