[Linux-Xtensa] Re: Cache flushing when transitioning from U-Boot to Kernel

Max Filippov jcmvbkbc at gmail.com
Thu Jul 11 19:30:21 PDT 2013


Hi Chris,

On Thu, Jul 11, 2013 at 10:16 PM, czankel <chris at zankel.net> wrote:
> In the current situation, the U-Boot version I've been working on doesn't
> flush the caches, and the kernel invalidates (not write-back!) all caches,
> so data still in the data cache can be lost (in fact, it is).  The options
> are:
>
> 1. Any boot loader, reset vector, etc. flushes the caches (write-back)
> 2. The kernel uses write-back instead of invalidate
>
> I haven't seen any other architecture flushing the caches in U-Boot, and it
> feels to me that when you jump to the kernel, any loader (or reset vector)
> would already have initialized the caches, so there's really no need to do

AFAIK ARM and some exotic arches start with caches disabled and
initialize them in boot/compressed/head.S

> anything in the kernel? In cases where we (re-) initialize the MMU, we
> probably need to flush the caches before messing with the MMU?

Looks like we can move cache unlock+invalidation to reset vector and
do nothing in kernel/head.S

-- 
Thanks.
-- Max


More information about the linux-xtensa mailing list