[Linux-Xtensa] RAM load/store reorder

Baruch Siach baruch at tkos.co.il
Wed Nov 27 18:54:57 UTC 2013


Hi Marc,

Thanks for you prompt response.

On Wed, Nov 27, 2013 at 08:39:25AM -0800, Marc Gauthier wrote:
> Baruch Siach wrote:
> > 1. Why is this seemingly NOP store/load pair at 0x5f3d414 and 0x5f3d416 
> > needed at all?
> 
> Looks like you're compiling at -O0.  In that case, the compiler
> ensures that all variables are in memory at every source line
> boundary ie. nothing is cached in registers across such boundaries,
> so debuggers can access/modify variables in memory (eg. stack) only,
> and the right thing happens.

The source file in question builds with -Os. I checked this again by looking 
at the actual build command line. Also, a3 holds an internal function pointer, 
not a user set variable.

> > 2. How can I avoid this execution reorder?
> 
> I'd like to understand better.  Can you show exact values of
> a1, a3, *(a1+16) at each breakpoint?

Here it is:

(xt-gdb) info b
Num     Type           Disp Enb Address    What
5       hw breakpoint  keep y   0x05f3d410 in fdt_next_subnode at fdt.c:218
        breakpoint already hit 3 times
7       hw breakpoint  keep y   0x05f3d41d in fdt_next_subnode at fdt.c:225
        breakpoint already hit 3 times
(xt-gdb) c
Continuing.

Breakpoint 5, fdt_next_subnode (fdt=0x2000000, offset=1675900) at fdt.c:218
218     fdt.c: No such file or directory.
        in fdt.c
(xt-gdb) p/a $a3
$6 = 0x5f3d374 <fdt_next_node>
(xt-gdb) p/x $a1+16
$8 = 0x5feefd0
(xt-gdb) x/x 0x5feefd0
0x5feefd0:      0x85f39685
(xt-gdb) c
Continuing.

Breakpoint 7, 0x05f3d41d in fdt_next_subnode (fdt=0x2000000, offset=1675900) at fdt.c:225
225     in fdt.c
(xt-gdb) p/a $a3
$9 = 0x85f39685
(xt-gdb) x/x 0x5feefd0
0x5feefd0:      0x05f3d374

> Loads can be scheduled
> ahead of stores, but *not* ahead of stores to the same address
> (which seems to be the case you're implying, and would cause
> many bad things).  It's possible though unusual with FPGA boards,
> for failures to occur near the max frequency at which the FPGA
> bitstream was synthesized.  Or to get bad bitstreams.  Did you
> generate the FPGA bitstream yourself from the Xtensa Processor
> Generator, or obtain it elsewhere?  You might want to try with
> another bitstream (eg. generate another one, maybe at a lower
> frequency).  And contact Tensilica support.

The FPGA runs at 25MHz which I believe is nowhere near the limit of this 
board. I'll check here how exactly this bitstream was generated.

Thanks,
baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
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